Modern subscriber line transceivers typically use digitally implemented signal processing hardware which requires expensive high resolution analog-to-digital converters (ADC's) having a large dynamic range. Furthermore, in order to accommodate high bit rate transmission over the relatively limited bandwidth of subscriber loops, a single high bit-rate data stream is often split into multiple lower rate streams and each such stream is transmitted down a separate twisted pair channel and combined at the far end to reconstruct the original signal. For example, in a High Bit-Rate Digital Subscriber Line (HDSL) system, a 1.544 Mbit/sec T-1 data stream is transmitted over two channels each operating at a rate of 784 Kbit/sec (772 Kbit/sec of T-1 data plus 12 Kbit/sec of overhead). As a result, two transceivers are normally required at each end of the subscriber loop thereby implying a need for four high resolution ADC's per subscriber.
More particularly, in a typical digital subscriber line application, transceivers are located at the central office (CO) and at a remote terminal (RT) in the subscriber premises. The master timing source for such a system is supplied by the central office and the RT transceivers derive their timing information from the received signal. Thus, the RT transceivers are slaved to the CO transceiver's timing reference. Timing recovery in the RT transceivers is typically performed by phase-locked loops which generate a local clock whose frequency is identical to the frequency of the transmitter's clock in the CO transceiver. For systems such as HDSL, which use two channels to deliver the T-1 data, there are two receivers at each end of the loop with independent clock recovery loops. After all transceivers acquire synchronization, their clock recovery phase-locked loops will generate clocks whose frequencies are all identical to the frequency of the CO master clock. However, their timing phases may be different to optimally detect the received signals. These timing phase differences result from the fact that the propagation delays of the signals down the twisted pair channels vary depending on the particular configuration. Thus, the optimal phase of the respective receiver clocks may be different.
Time sharing a single high sample rate ADC to digitize multiple analog signals is commonly used in instrumentation systems having large dynamic range requirements. In such systems, if N signals are to be digitized at a sampling rate of F.sub.S samples/sec, then these N signals are multiplexed into a single ADC operating at a sampling rate of NF.sub.S samples/sec The sampling interval T=1/F.sub.S is therefore subdivided into N equal subintervals and each of the N analog signals is sequentially sampled by the ADC during each subinterval. Although the effective sampling rate of each analog signal is F.sub.S, there is a phase offset of d=1/NF.sub.S seconds between the samples in each channel. In other words, signal 1 will be sampled at times t=0,T,2T,3T, . . . , signal 2 will be sampled at times t=d, d+T,d+2T, d+3T, . . . , signal 3 will be sampled at times t=2d, 2d+T, 2d+2T, 2d+3T, . . . , and so forth. Since the phase at which each analog signal is sampled is unimportant in instrumentation systems, this technique is quite effective in reducing hardware complexity. However, such a multiplexing technique cannot be applied to digital subscriber line transceiver applications because it does not permit the sampling phases on the individual channels to be arbitrarily chosen. The optimal sampling phase for each received signal in an HDSL system must be independently determined, and even slight deviations from the optimum can significantly degrade receiver performance. As previously mentioned, in a typical HDSL system, all four transceivers are slaved to the same master clock and therefore all operate at the same frequency. However, to achieve optimum performance, the individual receiver sampling phases must be independently determined by separate clock recovery phase-locked loops inasmuch as two received signals at a common end of the loop could, in the worst case, require identical sampling phases. In such a situation, it would not be possible to use a single conventionally multiplexed ADC to sample both received signals simultaneously.